1. Field of the Invention
The present invention relates to static random access memory (SRAM) cells. More specifically, the present invention relates to five transistor SRAM cells and methods for operating these cells in an array.
2. Discussion of Related Art
FIG. 1 is a circuit diagram of a conventional six-transistor SRAM cell 100. SRAM cell 100 includes n-channel access transistors 101-102, a first inverter 111 (which includes p-channel transistor 103 and n-channel transistor 104), a second inverter 112 (which includes p-channel transistor 105 and n-channel transistor 106), complementary bit lines 121-122, and word line 123. The operation of SRAM cell 100 is well documented in numerous resources, including, for example, Prince, Semiconductor Memories (2nd Edition, 1991), pp. 157-159. In general, SRAM cell 100 is accessed through both of access transistors 101-102 during read and write operations. Accessing SRAM cell 100 in this manner results in a relatively stable SRAM cell during both read and write operations. However, a relatively large layout area is required for the six transistors of SPAM cell 100. It would therefore be desirable to have an SRAM cell that requires fewer than six transistors, but has the same stability as a six-transistor SRAM cell.
FIG. 2 is a circuit diagram of a conventional five-transistor SRAM cell 200. As used herein, a five-transistor SRAM cell is defined as an SRAM cell that includes only five-transistors and no other circuit elements, such as diodes or resistors. SRAM cell 200 includes n-channel access transistor 201, inverters 211-212, nodes A and B, bit line 220 and word line 230. Inverter 211 includes p-channel transistor 203 and n-channel transistor 204. Similarly, inverter 212 includes p-channel transistor 205 and n-channel transistor 206.
To write a logical 1 to SRAM cell 200, the V.sub.CC supply voltage is applied to both bit line 220 and word line 230. Under these conditions, n-channel access transistor 201 is turned on, and a voltage equal to V.sub.CC -V.sub.TH is applied to node A, where V.sub.TH is the threshold voltage of access transistor 201.
To write a logical 0 to SRAM cell 200, the V.sub.CC supply voltage is applied to word line 230, and the V.sub.SS supply voltage is applied to bit line 220. Under these conditions, n-channel access transistor 201 is turned on, and a voltage equal to the V.sub.SS supply voltage is applied to node A.
To read SRAM cell 200, the V.sub.CC supply voltage is applied to word line 230, and a read voltage is applied to bit line 220. This read voltage must not be so high as to write a logical 1 to SRAM cell 200 during the read operation. Similarly, this read voltage must not be so low as to write a logical 0 to SRAM cell 200. Normal temperature variations, voltage variations and process variations in SRAM cell 200 typically result in an inadequate margin for providing an appropriate read voltage in SRAM cell 200.
To compensate for the inadequate margin available for the read voltage, a boosted voltage has been applied to word line 230 during a write operation. This boosted voltage is greater than the V.sub.CC supply voltage. During a read operation, the V.sub.CC supply voltage is applied to word line 230. While this provides SRAM cell 200 with an acceptable operating margin, access transistor 201 must be fabricated with a relatively thick gate oxide in order to withstand the boosted voltage applied to word line 230. This thicker gate oxide undesirably increases the complexity of the process used to fabricate SRAM cell 200.
In addition, applying the boosted voltage to word line 230 necessarily results in write conditions in every SRAM cell coupled to word line 230. Thus, the number of SRAM cells coupled to word line 230 is limited by the byte width of the associated array. That is, if the byte width of an associated array is 8-bits, then only 8 SRAM cells can be coupled to word line 230. The resulting array is therefore much narrower than desired.
It would therefore be desirable to have a five-transistor SRAM cell that operates in a stable manner with a single voltage applied to the gate of the access transistor during both read and write operations. It would further be desirable to have a five-transistor SRAM cell that can be incorporated in an array, such that the number of SRAM cells coupled to each word line in the array is greater than the width of a byte in the array.